| 2012 | A 15-GHz COMS multiphase rotary traveling-wave voltage-controlled oscillator | 박성민 | Article |
| 2015 | A 16-channel CMOS inverter transimpedance amplifier array for 3-D image processing of unmanned vehicles | 박성민 | Article |
| 2006 | A 1Gb/s 4-channel optical transceiver chipset for automotive wired networks | 박성민 | Conference Paper |
| 2007 | A 1Gb/s optical transceiver array chipset for automotive wired interconnects | 박성민 | Conference Paper |
| 2011 | A 1μm diameter tip fiber-based surface plasmon resonance system for single unit optical neural recording | 전상범 | Conference Paper |
| 2007 | A 2.5Gb/s ESD-protected dual-channel optical transceiver array | 박성민 | Conference Paper |
| 2010 | A 20-Gb/s transformer-based current-mode optical receiver in 0.13- μm CMOS | 박성민 | Article |
| 2023 | A 208-MHz, 0.75-mW Self-Calibrated Reference Frequency Quadrupler for a 2-GHz Fractional-N Ring-PLL in 4-nm FinFET CMOS | 박성민 | Article |
| 2020 | A 3-dimensional Modified Vernier Time-to-digital Converter for LiDAR Sensors | 박성민 | Article |
| 2014 | A 3.125-to-22-Gb/s multi-rate clock and data recovery using voltage-regulated active filter | 박성민 | Letter |
| 2007 | A 4-channel 12.5Gb/s common-gate transimpedance amplifier array for DVI/HDMI applications | 박성민 | Conference Paper |
| 2017 | A 4-Channel 6.25-Gb/s/ch VCSEL driver for HDMI 2.0 active optical cables | 박성민 | Article |
| 2018 | A 4-Channel 8-Gb/s/ch VCSEL driver array | 박성민 | Article |
| 2019 | A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS | 박성민; 김지훈 | Article |
| 2022 | A 46-nF/10-MΩ Range 114-aF/0.37-Ω Resolution Parasitic-and Temperature-Insensitive Reconfigurable RC-to-Digital Converter in 0.18-μm CMOS | 김지훈 | Article |
| 2009 | A 4Gb/s current-mode optical transceiver in 0.18μm CMOS | 박성민 | Conference Paper |
| 2004 | A 5-Gb/s 1/8-rate CMOS clock and data recovery circuit | 박성민 | Conference Paper |
| 2006 | A 5.2-mW, 2.5-Gb/s limiting amplifer for OC-48 SONET applications | 박성민 | Conference Paper |
| 2015 | A 6.6 mW, -94 dBc/Hz, 1.0-to-4.5 GHz phase-lock loop in 65-nm CMOS | 박성민 | Conference Paper |
| 2019 | A Band-Engineered One-Transistor DRAM With Improved Data Retention and Power Efficiency | 신형순 | Article |
